28C256 PDF

A Max. It requires a simple interface for in-system programming. Additionally, the CAT28C features hardware and software write protection. Characteristics subject to change without notice 1 Doc.

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When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention in their system. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a poll- ing operation. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 addi- tional bytes. If the tBLC limit is ex- ceeded the AT28C will cease accepting data and com- mence the internal programming operation.

All bytes dur- ing a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin.

DATA Polling may begin at anytime during the write cycle. Reading the toggle bit may begin at any time during the write cycle. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes.

When enabled, the software data protection SDP , will prevent inadvertent writes. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses refer to Software Data Protection Algorithm. After writing the 3-byte command sequence and after tWC the entire AT28C will be pro- tected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C This is done by pre- ceding the data to be written by the same 3-byte command sequence used to enable SDP.

Once set, SDP will remain active unless the disable com- mand sequence is issued. All command se- quences must conform to the page write timing specifica- tions. The data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers.

No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations.


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